A scheme for write before erase (pre-write) in a non-volatile memory has conventionally been known.
For example, a flash erase non-volatile memory described in Japanese Patent Laying-Open No. 10-64288 (PTD 1) carries out write before erase by successively updating an address of a memory cell array (1) while a first write-before-erase end signal (FWE) is at an inactive level. Then, this memory carries out verify for each address when an active level is set, and carries out control such that write before erase (pre-write) and verify is carried out only on an address at which a result of verify has indicated failure.
A semiconductor non-volatile memory described in Japanese Patent Laying-Open No. 11-144476 (PTD 2) performs a pre-write operation for reading a plurality of memory cells defined as an erase unit in at least a memory array in an erase operation mode and setting a state of write of a prescribed amount by repetition of a unit write operation and a write determination operation onto memory cells where charges are not accumulated in floating gates. Then, this memory performs an erase operation for setting to a state of erase of a prescribed amount by repetition of a unit erase operation and an erase determination operation in a batch under an erase reference voltage onto the plurality of memory cells defined as the erase unit. This memory performs a write operation for setting to a state of write of a prescribed amount by repetition of a unit write operation and a write determination operation onto a selected memory cell in a write operation mode.